1. Field of the Invention
The present invention relates to a semiconductor device which is a packaged semiconductor chip.
2. Description of the Related Art
FIG. 7 is a perspective view, partially broken away to show the internal structure, of a conventional quad-flat-packaged (QFP) semiconductor device. FIG. 8 is a cross-sectional view illustrating mounting of the semiconductor device of FIG. 7 on a printed-circuit board. The QFP semiconductor device is of the type in which the leads are located on the four side surfaces of the package.
A semiconductor device 1 includes a semiconductor chip 2 packaged in a molding resin 6 which forms the package. The semiconductor chip 2 is die bonded to a die pad 3 with a soldering material 3a. The semiconductor chip 2 has a plurality of electrode pads 2a on the peripheral edge of an upper surface thereof. A plurality of leads 4, each including an inner lead 4a located within the molding resin 6 and an outer lead 4b exposed from the molding resin 6, are provided around the semiconductor chip 2. An inner end portion 4c of each of the inner leads 4a is electrically connected to a corresponding electrode pad 2a on the semiconductor chip 2 by a thin metal wire 5 made of, for example, gold (Au) or the like.
To join the thin metal wire 5 to the inner end portions 4c of each of the inner leads 4a, each inner end portions 4c is plated, such as with silver (Ag). The outer lead 4b of each of the leads 4 which is exposed from the molding resin 6 is curved in a desired form.
The semiconductor device 1 arranged in the manner described above is mounted on a printed circuit board 7, as shown in FIG. 8. On the printed circuit board 7, a plurality of lands 8 are located at positions corresponding to the outer leads 4b of the semiconductor device 1 to be mounted thereon. The lands 8 are connected to an interconnection pattern (not shown), and the outer end portion of each of the outer leads 4b of the semiconductor device 1 is connected and fixed to the corresponding land 8 by solder 9. To mount the semiconductor device 1 on the printed circuit board 7, a solder paste is applied to the printed circuit board 7 by screen printing or the like, the semiconductor device 1 is mounted on the printed circuit board 7 together with other electric parts (not shown), and then the entirety is heated to melt the solder and thereby mount the semiconductor device. The interconnections formed in the printed circuit board 7 include a grounding line 10a and a power supply line 10b.
In the aforementioned conventional semiconductor device, the leads are fanned out on the same plane as that of the semiconductor chip. Consequently, as the number of leads increases, the length through which the leads are extended also increases. The leads may be extended, for example, 10 mm or more. Hence, the length of the power supply lead and the grounding lead, which should have a low inductance, increases, precluding a reduction in the inductance. Furthermore, if it is desired to increase the width of the power supply lead and the grounding lead in order to reduce the inductance thereof, fan out of the other signal leads is made impossible. This results in a reduction in the number of leads.